With the development of information processing technology in recent years, it is anticipated that many CPUs (Central Processing Units) will be incorporated in information processors of the future. However, there is concern that the development of the miniaturization of semiconductors, which is the basis for this information processing technology, will detract from the reliability of information processors such as semiconductor integrated circuits. Accordingly, the realization of both higher information processing performance and higher reliability will be indispensable to information processors having a multiplicity of processors.
FIG. 1 shows an example of the configuration of a typical information processor that uses two CPUs to raise performance and reliability.
The information processor shown in FIG. 1 is provided with CPUs 10000A and 10000B, comparator 11000, and bus 12000. When higher reliability is necessary, bus access of CPUs 10000A and 10000B is monitored by operating comparator 11000 that is provided between bus 12000 and CPUs 10000A and 10000B. During monitoring, reliability is improved by implementing a recovery process when disagreement occurs between CPUs 10000A and CPU 10000B. On the other hand, when higher performance is necessary, parallel processing is implemented using CPUs 10000A and 10000B without operating comparator 11000. In this way, a device that achieves both high performance and high reliability can be realized in a device that is provided with a plurality of CPUs (for example, refer to JP-A-2006-302289).
However, the above-described device suffers from the drawback that reliability can be improved only between CPUs that have been determined in advance. An additional problem is the waste of a large amount of wiring resources and area for just the connections between the outputs of the CPUs and the comparator when there is an extremely large number of CPUs. A further problem that accompanies this case is the increase in cost expended in the device.
It has thus been problematic to realize switching between a high-reliability mode and a high-performance mode at low cost between any of the CPUs in a device that includes a multiplicity of CPUs connected by an interconnected network.